1. Technical Field
The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly to a semiconductor device package including two molding layers having different coefficients of thermal expansion disposed over two opposite surfaces of a circuit layer and a method for manufacturing the same.
2. Description of the Related Art
A three-dimensional (3D) semiconductor device package may be subject to warpage due to its asymmetrical structure and characteristic mismatch between structural layers, such as a mismatch of coefficients of thermal expansion (CTE).
To alleviate warpage, a thickness of the semiconductor package may be increased. However, an increase in thickness of the semiconductor device package presents a conflict with the trend towards minimizing the sizes of electronic products.